Categories for Extreme Programming

Mass programming Essay

Mass programming Essay

PLDs are standard ICs, available in standard configurations. They are sold in high volume to many different customers. PLDs may be configured or programmed to create a part customized to a specific application. They have a single large block of programmable interconnect and consist of a matrix of logic macrocells that usually consists of programmable array logic followed by a flip-flop or latch. Types of PLDs are PROM, EPROM, PAL and PLA. PROM uses metal fuse that can be blown permanently.

EPROM uses programmable MOS transistors whose characteristics are altering by applying a high voltage.

PAL or Programmable Array Logic consists of a programmable AND logic array or AND plane, and fixed OR plane. PLA or Programmable Logic Array has a programmable AND plane followed by programmable OR plane. Based on type of programming PLDs may be classified as Erasable PLD (EPLD) and Mask-programmed PLD. It is characterized by customized mask layer and logic cells (Smith, 1997: 14). (Smith, 1997) Advantages Fast design turnaround.

Disadvantages Mass programming is not possible. It is more complex than PLDs. A field programmable gate array is a VLSI circuit that can be programmed in the user’s location.

A typical FPGA consists of an array of hundreds or thousands of logic blocks surrounded by programmable input and output blocks and connected together via programmable interconnections. There is a wide variety of internal configuration within these devices. The performance of each device depends on the circuit contained in their logic blocks and their efficiency of their programmed inter connections. Here none of mask layers are customized. There exists a method for programming basic cells and the interconnect. The core of FPGA is a regular array of combinational and sequential programmable basic logic cells.

It has a matrix of programmable interconnect that surrounds the basic cells and programmable I/O cells around the core. A typical FPGA block consists of look up tables, multiplexers, gates and flipflops. The look up table is a truth table stored in a SRAM and provides a combinational circuit functions for the logic blocks. These functions are realized from the truth table stored in the SRAM (Smith, 1997: 16). (Smith, 1997) Advantages Design turnaround is a few hours The truth table can be re-programmable. Easy to layout on PCBs. Disadvantages

The memory is volatile and presents the need for the look up table content to be reloaded when power is disrupted. Routing is easily blocked. The design requires extensive CAD tools to facilitate the synthesis procedure. FPGAs may be broadly classified as homogenous and heterogeneous FPGAs. As the name implies homogenous consists of only one type of logic cell and heterogeneous contains different types of logic cells. They can also be classified as Island type, Hierarchical and Row based FPGAs. Island Type FPGA It is common to Xilinx and Altera.

Here, the logic blocks are arranged in a matrix form. They are interconnected by horizontal and vertical routing wires. The routing wires are connected using programmable routing switches. (Sharma, 2005) Hierarchical FPGAs It comprises of a tree based interconnect structure. The leaves represent logic blocks. Two types of connecting boxes are present. The hexagon shaped boxes represent non compressing switches (no. of root going tracks = twice the no. of incoming tracks) and the diamond shaped boxes represent compressing switches (no. of root going tracks = no. of incoming tracks).